The present invention relates to methods of making microelectronic packages, apparatus therefor, and methods of making apparatus therefor.
The semiconductor chip packaging industry is a highly competitive business in which the packaging companies are waging an ongoing battle to reduce the costs associated with packaging their own chips and, many times, the chips owned by other parties. New technologies are constantly being investigated in order to reduce the packaging cost while producing packaging structures and processes which produce similar or superior results. Further, there is on-going pressure from the electronic industry to reduce the internal impedances of semiconductor packages so that the semiconductor makers may increase the speed of their chips without experiencing significant signal degradation thereby decreasing the processing and/or response time a user of a finished electronic product will encounter when requesting the electronic product to perform a given task. Further still, the electronic industry requires that the chips are packaged in smaller and smaller form factors so that the packaged chips take up less space on a supporting circuitized substrate (such as a printed wiring board, “PWB”). It is also important that the thickness dimension of the packaged chips is reduced so that the same operational circuitry may be fit into a smaller area thereby allowing for more portability (size, weight, etc.) for the resulting finished electronic product and/or allowing for an increase in a product's processing power without also increasing its size. As the packaged chips are made smaller and placed closer and closer together on the PWB, the chips will produce more heat and will receive more heat from the adjacent chips. It is therefore also very important to provide a direct thermal path to facilitate the removal of heat from the packaged chips.
In certain embodiments of U.S. Pat. No. 6,001,671, the disclosure of which is hereby incorporated by reference herein, pads are formed on a sacrificial layer and a semiconductor chip is assembled with the sacrificial layer. After disposing an encapsulant over the microelectronic element and pads, the sacrificial layer is removed, leaving a packaged chip including the pads. The pads are formed on the sacrificial layer by selectively electroplating metal pads onto the sacrificial layer.
Despite this effort in the art, improvements in packaging microelectronic elements are desired.